Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process

T. W. Kim, B. D. Choi, D. K. Kim

Research output: Contribution to journalArticle

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Abstract

An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.

Original languageEnglish
Pages (from-to)876-877
Number of pages2
JournalElectronics Letters
Volume50
Issue number12
DOIs
Publication statusPublished - 2014 Jun 5

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