Performance re-engineering of embedded real-time systems

Minsoo Ryu, Jungkeun Park, Kimoon Kim, Yangmin Seo, Seongsoo Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new realtime throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.

Original languageEnglish
Title of host publicationProceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999
PublisherAssociation for Computing Machinery
Pages80-86
Number of pages7
ISBN (Electronic)1581131364, 9781581131369
DOIs
StatePublished - 1999 May 1
Event1999 ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999 - Atlanta, United States
Duration: 1999 May 5 → …

Publication series

NameProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
VolumePart F129197

Other

Other1999 ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999
CountryUnited States
CityAtlanta
Period99/05/5 → …

Fingerprint

Real time systems
Embedded systems
Hardware
Throughput
Costs
Systems analysis
Scheduling
Processing

Cite this

Ryu, M., Park, J., Kim, K., Seo, Y., & Hong, S. (1999). Performance re-engineering of embedded real-time systems. In Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999 (pp. 80-86). (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES); Vol. Part F129197). Association for Computing Machinery. https://doi.org/10.1145/314403.314454
Ryu, Minsoo ; Park, Jungkeun ; Kim, Kimoon ; Seo, Yangmin ; Hong, Seongsoo. / Performance re-engineering of embedded real-time systems. Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999. Association for Computing Machinery, 1999. pp. 80-86 (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)).
@inproceedings{0108acd9b27a44788fb6235a4c383964,
title = "Performance re-engineering of embedded real-time systems",
abstract = "This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new realtime throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.",
author = "Minsoo Ryu and Jungkeun Park and Kimoon Kim and Yangmin Seo and Seongsoo Hong",
year = "1999",
month = "5",
day = "1",
doi = "10.1145/314403.314454",
language = "English",
series = "Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)",
publisher = "Association for Computing Machinery",
pages = "80--86",
booktitle = "Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999",

}

Ryu, M, Park, J, Kim, K, Seo, Y & Hong, S 1999, Performance re-engineering of embedded real-time systems. in Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999. Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), vol. Part F129197, Association for Computing Machinery, pp. 80-86, 1999 ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999, Atlanta, United States, 99/05/5. https://doi.org/10.1145/314403.314454

Performance re-engineering of embedded real-time systems. / Ryu, Minsoo; Park, Jungkeun; Kim, Kimoon; Seo, Yangmin; Hong, Seongsoo.

Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999. Association for Computing Machinery, 1999. p. 80-86 (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES); Vol. Part F129197).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Performance re-engineering of embedded real-time systems

AU - Ryu, Minsoo

AU - Park, Jungkeun

AU - Kim, Kimoon

AU - Seo, Yangmin

AU - Hong, Seongsoo

PY - 1999/5/1

Y1 - 1999/5/1

N2 - This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new realtime throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.

AB - This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. The re-engineering of an embedded system is defined as a development task of meeting newly imposed performance requirements after its hardware and software have been fully implemented. The performance requirements may include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. Inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new realtime throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck processes in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance scaling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirements. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.

UR - http://www.scopus.com/inward/record.url?scp=85028887829&partnerID=8YFLogxK

U2 - 10.1145/314403.314454

DO - 10.1145/314403.314454

M3 - Conference contribution

AN - SCOPUS:85028887829

T3 - Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

SP - 80

EP - 86

BT - Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999

PB - Association for Computing Machinery

ER -

Ryu M, Park J, Kim K, Seo Y, Hong S. Performance re-engineering of embedded real-time systems. In Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 1999. Association for Computing Machinery. 1999. p. 80-86. (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)). https://doi.org/10.1145/314403.314454