Dynamic RAM (DRAM) is mainly used as the main memory. As the DRAM density increases, the address bus width required for a DRAM device is also increased. However, in a high-speed DRAM interface, as the address bus becomes wider, not only the routing area and power consumption increase but also the timing margin to maintain signal integrity also decreases. Furthermore, without increasing the address bus pins, row addressing may need multiple cycles, which will lead to significant performance degradation. In this Letter, the authors propose a novel row addressing scheme to issue single-cycle row addressing without extra address bus pins for high-density DRAM devices. The proposed scheme prefetches a part of the target row address for the next activate command using unused address bus of a precharge command. The proposed scheme also enables an auto-activate operation which activates automatically after precharge without explicitly issuing an activate command. As a result, the proposed row addressing scheme reduces the performance degradation due to multi-cycle row addressing and the power consumption on the memory bus due to explicit activate command.