Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

Ki-Seok Chung, C. L. Liu

Research output: Contribution to conferencePaper

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Abstract

In this paper, we present several optimization techniques for power reduction utilizing circuit symmetries. There are four kinds of symmetries that we detect in a given circuit implementation. First, we propose an algorithm for detecting the four different types of symmetries in a given circuit implementation of a Boolean function. Several re-synthesis techniques utilizing such symmetries are proposed. These techniques enable us to optimize power consumption and delay with no (or very little) area overhead. We have carried out experiments on MCNC benchmark circuits to demonstrate the efficiency of the proposed techniques. The average power reduction is 14% with little or none area and/or delay overhead.

Original languageEnglish
Pages215-220
Number of pages6
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: 1998 Aug 101998 Aug 12

Other

OtherProceedings of the 1998 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period98/08/1098/08/12

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Chung, K-S., & Liu, C. L. (1998). Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction. 215-220. Paper presented at Proceedings of the 1998 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, .