Impact of processor cache memory on storage performance

Young Kuen Kim, Yong Ho Song

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently flash memory provides high performance, high capacity, and stable quality of service (QoS). To satisfy these features, a complex Flash Translation Layer (FTL) algorithm is used, which greatly increases the amount of data processed by the processor. As a result, data traffic increases between processor and cache memory, resulting in more cache misses. Frequent cache misses cause cache miss penalty to degrade overall storage performance. In this paper, we analyze the effect of cache size on storage devices. As a result of verifying the performance on the FPGA board, when the cache size increased from 2KB to 16KB, the performance increase was 273.8% for random write, 214.4% for random read, 281.6% for sequential write, and 313.3% for sequential read.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages304-305
Number of pages2
ISBN (Electronic)9781538622858
DOIs
StatePublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

Keywords

  • Cache
  • Flash translation layer
  • NAND flash memory
  • Processor

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  • Cite this

    Kim, Y. K., & Song, Y. H. (2018). Impact of processor cache memory on storage performance. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 304-305). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368908