Fabrication of a nonvolatile memory with double-stacked Au nano-crystals

Dong Uk Lee, Min Seung Lee, Eun Kyu Kim, Hyun Mo Koo, Won Ju Cho, Won Mok Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Nonvolatile memory devices with double-stacked Au nano-crystals on p-type (100) silicon-on-insulator wafers were fabricated and the electrical characteristics, such as the subthreshold property, the threshold voltage shift and the retention property, were analyzed. Here, the Au nano-crystals, the SiO 1.3N control and the tunnel oxides were deposited by reactive RF magnetron sputtering. The channel length and width of the nano-floating gate memory, which contained the double-stacked Au nano-crystals, were 20 μm. The memory window was about 1.23 V when the programming and erasing times of this memory device were approximately 500 μs and 5 ms, respectively. However, the memory window increased up to about 6 V when initial programming/erasing conditions were 20 V for 200 ms and -20 V for 500 ms and it was maintained at 2.7 V after 10 3 s.

Original languageEnglish
Pages (from-to)1824-1828
Number of pages5
JournalJournal of the Korean Physical Society
Volume54
Issue number5 PART 1
StatePublished - 2009 May 1

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fabrication
crystals
programming
threshold voltage
floating
tunnels
magnetron sputtering
insulators
wafers
oxides
shift
silicon

Keywords

  • Au
  • Nano-floating gate memory
  • SiON

Cite this

Lee, D. U., Lee, M. S., Kim, E. K., Koo, H. M., Cho, W. J., & Kim, W. M. (2009). Fabrication of a nonvolatile memory with double-stacked Au nano-crystals. Journal of the Korean Physical Society, 54(5 PART 1), 1824-1828.
Lee, Dong Uk ; Lee, Min Seung ; Kim, Eun Kyu ; Koo, Hyun Mo ; Cho, Won Ju ; Kim, Won Mok. / Fabrication of a nonvolatile memory with double-stacked Au nano-crystals. In: Journal of the Korean Physical Society. 2009 ; Vol. 54, No. 5 PART 1. pp. 1824-1828.
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abstract = "Nonvolatile memory devices with double-stacked Au nano-crystals on p-type (100) silicon-on-insulator wafers were fabricated and the electrical characteristics, such as the subthreshold property, the threshold voltage shift and the retention property, were analyzed. Here, the Au nano-crystals, the SiO 1.3N control and the tunnel oxides were deposited by reactive RF magnetron sputtering. The channel length and width of the nano-floating gate memory, which contained the double-stacked Au nano-crystals, were 20 μm. The memory window was about 1.23 V when the programming and erasing times of this memory device were approximately 500 μs and 5 ms, respectively. However, the memory window increased up to about 6 V when initial programming/erasing conditions were 20 V for 200 ms and -20 V for 500 ms and it was maintained at 2.7 V after 10 3 s.",
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Lee, DU, Lee, MS, Kim, EK, Koo, HM, Cho, WJ & Kim, WM 2009, 'Fabrication of a nonvolatile memory with double-stacked Au nano-crystals', Journal of the Korean Physical Society, vol. 54, no. 5 PART 1, pp. 1824-1828.

Fabrication of a nonvolatile memory with double-stacked Au nano-crystals. / Lee, Dong Uk; Lee, Min Seung; Kim, Eun Kyu; Koo, Hyun Mo; Cho, Won Ju; Kim, Won Mok.

In: Journal of the Korean Physical Society, Vol. 54, No. 5 PART 1, 01.05.2009, p. 1824-1828.

Research output: Contribution to journalArticle

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AU - Kim, Won Mok

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