Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure

Ju Tae Ryu, Sung Hwan Jang, Taewhan Kim

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Abstract

The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34% smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.

Original languageEnglish
Article number064306
JournalJapanese Journal of Applied Physics
Volume53
Issue number6
DOIs
StatePublished - 2014 Jan 1

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Flash memory
flash
augmentation
floating
programming
Electric fields
saturation
Data storage equipment
Oxides
oxides
electric fields
Electric potential
electric potential

Cite this

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title = "Enhancement of electrical characteristics of the coupling ratio and the program/erase operation for NAND flash memories with an asymmetric interpoly-dielectric structure",
abstract = "The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34{\%} smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.",
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AU - Kim, Taewhan

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AB - The electrical characteristics of NAND flash memories with an asymmetric interpoly-dielectric (IPD) structure and a conventional IPD structure were simulated by using a technology computer-aided sentaurus simulation tool to enhance their device performance. The floating gate potential and the on-current level of the NAND memory devices with an asymmetric IPD structure were higher than those with a conventional IPD structure. The maximum electric field formed at the rounding boundary area of the floating gate and the blocking oxide layer in an asymmetric IPD structure was 34% smaller than that in a conventional IPD structure. The trapped charges in the floating gate layer of NAND flash memories with an asymmetric IPD structure increased owing to an increase in the saturation voltage during programming and erasing operation.

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