Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM

Chunseok Jeong, Changsik Yoo, Jae Jin Lee, Joongsik Kih

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

A digital delay locked loop (DLL) for 1.2Gb/s/pin double data rate (DDR) SDRAM is described which incorporates duty cycle correction (DCC). The locking information of DCC is also stored as digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL implemented in a 0.35μm CMOS technology provides an output clock with 64ps peak-to-peak jitter and the accuracy of the DCC is ±0.7% for ±10% input duty error from 250MHz to 600MHz of clock frequency. The digital DLL excluding I/O buffers dissipates 10mW from a 2.5V power supply.

Original languageEnglish
Title of host publicationESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
EditorsM. Steyaert, C.L. Claeys
Pages379-382
Number of pages4
StatePublished - 2004 Dec 1
EventESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference - Leuven, Belgium
Duration: 2004 Sep 212004 Sep 23

Publication series

NameESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Other

OtherESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
CountryBelgium
CityLeuven
Period04/09/2104/09/23

Fingerprint

Clocks
Jitter
Electric power utilization

Cite this

Jeong, C., Yoo, C., Lee, J. J., & Kih, J. (2004). Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. In M. Steyaert, & C. L. Claeys (Eds.), ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference (pp. 379-382). (ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference).
Jeong, Chunseok ; Yoo, Changsik ; Lee, Jae Jin ; Kih, Joongsik. / Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference. editor / M. Steyaert ; C.L. Claeys. 2004. pp. 379-382 (ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference).
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title = "Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM",
abstract = "A digital delay locked loop (DLL) for 1.2Gb/s/pin double data rate (DDR) SDRAM is described which incorporates duty cycle correction (DCC). The locking information of DCC is also stored as digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL implemented in a 0.35μm CMOS technology provides an output clock with 64ps peak-to-peak jitter and the accuracy of the DCC is ±0.7{\%} for ±10{\%} input duty error from 250MHz to 600MHz of clock frequency. The digital DLL excluding I/O buffers dissipates 10mW from a 2.5V power supply.",
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Jeong, C, Yoo, C, Lee, JJ & Kih, J 2004, Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. in M Steyaert & CL Claeys (eds), ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference. ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference, pp. 379-382, ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference, Leuven, Belgium, 04/09/21.

Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. / Jeong, Chunseok; Yoo, Changsik; Lee, Jae Jin; Kih, Joongsik.

ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference. ed. / M. Steyaert; C.L. Claeys. 2004. p. 379-382 (ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - A digital delay locked loop (DLL) for 1.2Gb/s/pin double data rate (DDR) SDRAM is described which incorporates duty cycle correction (DCC). The locking information of DCC is also stored as digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL implemented in a 0.35μm CMOS technology provides an output clock with 64ps peak-to-peak jitter and the accuracy of the DCC is ±0.7% for ±10% input duty error from 250MHz to 600MHz of clock frequency. The digital DLL excluding I/O buffers dissipates 10mW from a 2.5V power supply.

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Jeong C, Yoo C, Lee JJ, Kih J. Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. In Steyaert M, Claeys CL, editors, ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference. 2004. p. 379-382. (ESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference).