Controlling die warpage by applying under bump metallurgy for fan-out package process applications

Hwan Pil Park, Young-Ho Kim, Young Moon Jang, Sung Hoon Choa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 μm, 5 μm, and 7 μm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moiré measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.

Original languageEnglish
Title of host publicationProceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1912-1919
Number of pages8
ISBN (Print)9781538649985
DOIs
StatePublished - 2018 Aug 7
Event68th IEEE Electronic Components and Technology Conference, ECTC 2018 - San Diego, United States
Duration: 2018 May 292018 Jun 1

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2018-May
ISSN (Print)0569-5503

Other

Other68th IEEE Electronic Components and Technology Conference, ECTC 2018
CountryUnited States
CitySan Diego
Period18/05/2918/06/1

Fingerprint

Metallurgy
Fans
Polyimides
Soldering alloys
Copper
Silicon
Metallizing
Silicon wafers
Oxides
Solidification
Molten materials
Packaging

Keywords

  • Backsided under bump metallurgy
  • Die Warpage control
  • Fan-out package

Cite this

Park, H. P., Kim, Y-H., Jang, Y. M., & Choa, S. H. (2018). Controlling die warpage by applying under bump metallurgy for fan-out package process applications. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018 (pp. 1912-1919). [8429799] (Proceedings - Electronic Components and Technology Conference; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2018.00286
Park, Hwan Pil ; Kim, Young-Ho ; Jang, Young Moon ; Choa, Sung Hoon. / Controlling die warpage by applying under bump metallurgy for fan-out package process applications. Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1912-1919 (Proceedings - Electronic Components and Technology Conference).
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abstract = "We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 μm, 5 μm, and 7 μm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moir{\'e} measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.",
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Park, HP, Kim, Y-H, Jang, YM & Choa, SH 2018, Controlling die warpage by applying under bump metallurgy for fan-out package process applications. in Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018., 8429799, Proceedings - Electronic Components and Technology Conference, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., pp. 1912-1919, 68th IEEE Electronic Components and Technology Conference, ECTC 2018, San Diego, United States, 18/05/29. https://doi.org/10.1109/ECTC.2018.00286

Controlling die warpage by applying under bump metallurgy for fan-out package process applications. / Park, Hwan Pil; Kim, Young-Ho; Jang, Young Moon; Choa, Sung Hoon.

Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1912-1919 8429799 (Proceedings - Electronic Components and Technology Conference; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 μm, 5 μm, and 7 μm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moiré measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.

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T3 - Proceedings - Electronic Components and Technology Conference

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Park HP, Kim Y-H, Jang YM, Choa SH. Controlling die warpage by applying under bump metallurgy for fan-out package process applications. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1912-1919. 8429799. (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2018.00286