Clock- and data-recovery circuit with independently controlled eye-tracking loop for high-speed graphic drams

Jun Yong Song, Oh Kyong Kwon

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18-μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 2 31-1 pseudorandom binary-sequence input.

Original languageEnglish
Article number5940211
Pages (from-to)422-426
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume58
Issue number7
DOIs
StatePublished - 2011 Jul 1

Fingerprint

Clock and data recovery circuits (CDR circuits)
Jitter
Clocks
Recovery
Binary sequences
Bit error rate

Keywords

  • Bang-bang phase detector (PD)
  • clock and data recovery (CDR)
  • complementary metal-oxide-semiconductor (CMOS)
  • dynamic random access memory (DRAM)
  • eye tracking
  • jitter tolerance

Cite this

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abstract = "An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18-μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 2 31-1 pseudorandom binary-sequence input.",
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Clock- and data-recovery circuit with independently controlled eye-tracking loop for high-speed graphic drams. / Song, Jun Yong; Kwon, Oh Kyong.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 7, 5940211, 01.07.2011, p. 422-426.

Research output: Contribution to journalArticle

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