Algorithm for synthesis of system-level interface circuits

Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm.

Original languageEnglish
Pages (from-to)442-447
Number of pages6
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - 1996 Dec 1
EventProceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: 1996 Nov 101996 Nov 14

Fingerprint

Networks (circuits)
Interfaces (computer)
Inductive logic programming (ILP)
Glues
Logic circuits
Electric wiring
Application specific integrated circuits
Embedded systems
Software packages
Microprocessor chips
Electric power utilization
Data storage equipment

Cite this

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Algorithm for synthesis of system-level interface circuits. / Chung, Ki-Seok; Gupta, Rajesh K.; Liu, C. L.

In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 01.12.1996, p. 442-447.

Research output: Contribution to journalConference article

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