A Static Power Saving TTL-to-CMOS Input Buffer

Changsik Yoo, Min Kyu Kim, Wonchan Kim

Research output: Contribution to journalArticle

4 Scopus citations


This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 µm CMOS process, and the through current is measured to be only 8.9 µA and 11.7 µA. for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output upto 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation [1].

Original languageEnglish
Pages (from-to)616-620
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - 1995 May

Fingerprint Dive into the research topics of 'A Static Power Saving TTL-to-CMOS Input Buffer'. Together they form a unique fingerprint.

  • Cite this