This brief proposes a small-area and energy-efficient 12-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors with a column-parallel readout structure. The proposed SA-ADC, which uses only a 6-bit capacitor digital-to-analog converter (DAC) for residue sampling, reduces the capacitor area to 1/64th of that for the 12-bit capacitor DAC and adopts the scaled reference voltages for 12-bit conversion. It also achieves 88% lower switching energy of the capacitor DAC compared with the 12-bit SA-ADC with split capacitor structure. A foreground digital calibration is employed to compensate for the linearity error caused by the inaccurately scaled reference voltages. A test chip, which has 100 readout channels with the proposed SA-ADC, is fabricated using a 0.18-μm CMOS process. The measurement results show that the proposed SA-ADC with the proposed digital calibration has differential nonlinearity (DNL) of -0.8/+1.7 LSB and integral nonlinearity (INL) of -2.3/+2.4 LSB, and without the calibration, it has DNL of -1/+14.9 LSB and INL of -15.8/+12.7 LSB. In addition, a digital correlated double sampling method improves the standard deviation of the readout channel outputs from 62.1 to 1.4 LSB.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - 2015 Oct 1|
- CMOS image sensor (CIS)
- column-parallel readout
- foreground digital calibration
- successive approximation analog-to-digital converter (SA-ADC)