TY - JOUR
T1 - A novel structure and operation scheme of vertical channel nand flash with ferroelectric memory for multi string operations
AU - Choi, Seonjun
AU - Choi, Changhwan
AU - Jeong, Jae Kyeong
AU - Kang, Myounggon
AU - Song, Yun Heub
N1 - Publisher Copyright:
© 2020 by the authors.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2021/1
Y1 - 2021/1
N2 - In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.
AB - In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.
KW - Ferroelectric memory
KW - GIDL
KW - Polysilicon
KW - Vertical channel NAND flash
UR - http://www.scopus.com/inward/record.url?scp=85098542316&partnerID=8YFLogxK
U2 - 10.3390/electronics10010032
DO - 10.3390/electronics10010032
M3 - Article
AN - SCOPUS:85098542316
VL - 10
SP - 1
EP - 12
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
SN - 2079-9292
IS - 1
M1 - 32
ER -