It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in a SoC design increases, IP verification and performance validation have become the important factors in reducing time-to-market. In this paper, we propose a novel SoC platform based verification methodology which tests multiple IPs together using a single testbench. We've found that commercially available SoC platforms such as Altera Excalibur or Xilinx Virtex provide excellent environment in verifying the functionalities of mutually interactive multiple IPs with very low cost. In our methodology, embedded processor core built in the SoC device is used mainly for verification purposes and it runs a C-based testbench. The mutually interactive IPs are programmed in the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator. Using this platform, we have verified up to five IPs together successfully, but we can verify more IPs together easily. Time and effort to verify complex IPs have been significantly reduced using this methodology.
|Number of pages||12|
|Journal||International Journal of Information and Communication Technology|
|Publication status||Published - 2009 Jul 15|
- System on chip