A novel multi-ip verification methodology using an soc platform

Joo Yul Park, Ki-Seok Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in an SoC design increases, verifying multiple IPs together is really important to reduce time-to-market. In this paper, we propose a novel SoC platform based verification methodology which tests multiple IPs together using a single testbench. We've found that commercially available SoC platforms such as Altera Excalibur or Xilinx Virtex provide excellent environment in verifying the functionalities of mutually interactive multiple IPs with very low cost. In our methodology, embedded processor core built in the SoC device is used mainly for verification purposes, and it runs a C-based testbench. The mutually interactive IPs are programmed in the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator. Using this platform, we have verified up to 5 IPs together successfully. Time and effort to verify complex IPs have been significantly reduced using this methodology.

Original languageEnglish
Title of host publicationProceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008
Pages292-297
Number of pages6
StatePublished - 2008 Dec 1
Event4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008 - Langkawi, Malaysia
Duration: 2008 Apr 22008 Apr 4

Other

Other4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008
CountryMalaysia
CityLangkawi
Period08/04/208/04/4

Fingerprint

Application specific integrated circuits
Field programmable gate arrays (FPGA)
System-on-chip
Communication
Costs

Keywords

  • AMBA
  • FPGA
  • SoC
  • Verification

Cite this

Park, J. Y., & Chung, K-S. (2008). A novel multi-ip verification methodology using an soc platform. In Proceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008 (pp. 292-297)
Park, Joo Yul ; Chung, Ki-Seok. / A novel multi-ip verification methodology using an soc platform. Proceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008. 2008. pp. 292-297
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Park, JY & Chung, K-S 2008, A novel multi-ip verification methodology using an soc platform. in Proceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008. pp. 292-297, 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008, Langkawi, Malaysia, 08/04/2.

A novel multi-ip verification methodology using an soc platform. / Park, Joo Yul; Chung, Ki-Seok.

Proceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008. 2008. p. 292-297.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Park JY, Chung K-S. A novel multi-ip verification methodology using an soc platform. In Proceedings of the 4th IASTED International Conference on Advances in Computer Science and Technology, ACST 2008. 2008. p. 292-297