A new onchip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

Yungseon Eo, William R. Eisenstadt, Ju Young Jeong, Oh Kyong Kwon

Research output: Contribution to journalArticle

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Abstract

A new simple closedform crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further while existing models do not support the multiple line crosstalk behaviors our model can be generalized to multiple lines. That is unlike previously published work even if the geometrical structures are not identical it can accurately predict crosstalk. The model is experimentally verified with 0.35//m CMOS processbased interconnect test structures. The new model can be readily implemented in CAD analysis tools. Thereby this model can be used to predict the signal integrity for highspeed and highdensity VLSI circuit design.

Original languageEnglish
Number of pages1
JournalIEEE Transactions on Electron Devices
Volume47
Issue number1
Publication statusPublished - 2000 Dec 1

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Keywords

  • Crosstalk
  • Distributedmodel
  • Effectivecapacitance
  • Effectiveresistance
  • Interconnects
  • Lumpedmodel
  • Signalintegrity

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