A fREF/5 Bandwidth Type-II Charge-Pump Phase-Locked Loop with Dual-Edge Phase Comparison and Sampling Loop Filter

Kwang Soo Kim, Kyungmin Kim, Changsik Yoo

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to fREF/5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than-121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than-58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm2 silicon area.

Original languageEnglish
Article number8430518
Pages (from-to)825-827
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Volume28
Issue number9
DOIs
StatePublished - 2018 Sep 1

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Phase locked loops
Clocks
sampling
Pumps
pumps
Phase noise
Sampling
bandwidth
Bandwidth
filters
clocks
Variable frequency oscillators
voltage controlled oscillators
Feedback
Silicon
CMOS
prototypes
retarding
cycles
silicon

Keywords

  • CMOS
  • dual-edge phase comparison (DEPC)
  • phase-locked loop (PLL)
  • sampling loop filter (SLF)
  • type-II charge-pump (CP) PLL

Cite this

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title = "A fREF/5 Bandwidth Type-II Charge-Pump Phase-Locked Loop with Dual-Edge Phase Comparison and Sampling Loop Filter",
abstract = "The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to fREF/5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than-121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than-58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm2 silicon area.",
keywords = "CMOS, dual-edge phase comparison (DEPC), phase-locked loop (PLL), sampling loop filter (SLF), type-II charge-pump (CP) PLL",
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A fREF/5 Bandwidth Type-II Charge-Pump Phase-Locked Loop with Dual-Edge Phase Comparison and Sampling Loop Filter. / Kim, Kwang Soo; Kim, Kyungmin; Yoo, Changsik.

In: IEEE Microwave and Wireless Components Letters, Vol. 28, No. 9, 8430518, 01.09.2018, p. 825-827.

Research output: Contribution to journalArticle

TY - JOUR

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N2 - The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to fREF/5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than-121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than-58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm2 silicon area.

AB - The bandwidth (BW) of type-II charge-pump (CP) phase-locked loop (PLL) is extended to fREF/5 by dual-edge phase comparison (DEPC) to achieve better phase noise suppression of voltage-controlled oscillator. The reference spur that may result from the unequal duty cycles of reference clock and feedback clock is prevented by sampling loop filter (SLF). A prototype 1.25-GHz type-II CP-PLL employing the proposed DEPC and SLF has been implemented in a 65-nm CMOS technology and achieves 50-MHz BW with 250-MHz reference clock. The phase noise is smaller than-121 dBc/Hz at 1-MHz offset from the carrier, and the reference spur is smaller than-58.5 dBc. The type-II CP-PLL consumes 14.9 mW from a 1.2-V supply and occupies 0.107-mm2 silicon area.

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KW - phase-locked loop (PLL)

KW - sampling loop filter (SLF)

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