A new CMOS buffer without short-circuit power consumption is proposed. The gate- driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15 % smaller than conventional tapered CMOS buffer.
|Number of pages||3|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|State||Published - 2000 Dec 1|
- Cmos buffer
- Short-circuit power consumption