A CMOS buffer without short-circuit power consumption

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Abstract

A new CMOS buffer without short-circuit power consumption is proposed. The gate- driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15 % smaller than conventional tapered CMOS buffer.

Original languageEnglish
Pages (from-to)935-937
Number of pages3
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume47
Issue number9
DOIs
StatePublished - 2000 Dec 1

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Keywords

  • Cmos buffer
  • Short-circuit power consumption

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