A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28-40nm CMOS processes have been demonstrated for <20dB loss channels with energy efficiencies ranging from 4.4 to 11.96pJ/b. In order to support channels with higher losses, the half-rate 65nm receiver front-end design described in [3] includes a 3-tap DFE, a 2-tap FFE, and a CTLE at ∼2.88pJ/b, but neither closed-loop equalizer adaptation nor clock and data recovery were demonstrated. Closing these loops is especially critical in such an interleaved architecture, since at these data-rates each interleaved datapath can result in a noticeably different overall channel response (ISI), and the need for closed-loop CDR is self-evident. This paper therefore presents a fully adaptive 60Gb/s transceiver, supporting >20dB channel loss, implemented in a 65nm CMOS technology (Fig. 6.2.1). The full transceiver (including baud-rate CDR) achieves 60Gb/s and 4.8pJ/b energy efficiency over a 0.7m Twinax cable.

Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages112-113
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - 2017 Mar 2
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: 2017 Feb 52017 Feb 9

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period17/02/517/02/9

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    Han, J., Lu, Y., Sutardja, N., & Alon, E. (2017). A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 112-113). [7870286] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870286