The demand for ultra-high speed transceivers continues to explode, and while the data-rate for high-speed I/O standards has increased accordingly, the historically constant or even decreasing power budgets available for the transceivers push these designs to be extremely energy efficient. To begin addressing this need, recently published NRZ transceivers operating up to 56.5Gb/s with a 1-tap DFE and/or CTLE [1,2] in 28-40nm CMOS processes have been demonstrated for <20dB loss channels with energy efficiencies ranging from 4.4 to 11.96pJ/b. In order to support channels with higher losses, the half-rate 65nm receiver front-end design described in  includes a 3-tap DFE, a 2-tap FFE, and a CTLE at ∼2.88pJ/b, but neither closed-loop equalizer adaptation nor clock and data recovery were demonstrated. Closing these loops is especially critical in such an interleaved architecture, since at these data-rates each interleaved datapath can result in a noticeably different overall channel response (ISI), and the need for closed-loop CDR is self-evident. This paper therefore presents a fully adaptive 60Gb/s transceiver, supporting >20dB channel loss, implemented in a 65nm CMOS technology (Fig. 6.2.1). The full transceiver (including baud-rate CDR) achieves 60Gb/s and 4.8pJ/b energy efficiency over a 0.7m Twinax cable.