A 6-Gb/s Wireline Receiver with Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS

Hyochang Kim, Changsik Yoo

Research output: Contribution to journalArticle

Abstract

A receiver for a three-lane 6-Gb/s/lane serial link has been developed in 28-nm CMOS technology. It incorporates an intrapair skew compensator (IPSC) and a three-tap decision feedback equalizer (DFE). The IPSC removes the IPS in analog front end by adding differential and common-mode signals of a differential pair. The three-tap DFE is realized with clock and data recovery (CDR) circuit with minimum hardware complexity. The receiver consumes 31.0 mW/lane at 6 Gb/s/lane and occupies an active area of 0.08 mm2

Original languageEnglish
Article number8999809
Pages (from-to)1107-1117
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number5
DOIs
StatePublished - 2020 May 1

Keywords

  • Clock and data recovery (CDR)
  • CMOS
  • decision feedback equalizer (DFE)
  • intrapair skew (IPS)
  • wireline receiver

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