622Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

Inyeo Lee, Changsik Yoo, Wonchan Kim, Sanghoon Chai, Wonchul Song

Research output: Contribution to journalConference article

7 Citations (Scopus)

Abstract

A 622Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8μ CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200mW with a single 5V supply, whose core occupies 800×900μ2. RMS jitter of the recovered 78MHz clock is 46ps (0.36%).

Original languageEnglish
Pages (from-to)198-199
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume39
StatePublished - 1996 Feb 1
EventProceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1996 Feb 81996 Feb 10

Fingerprint

Phase locked loops
Clocks
Detectors
Recovery
Demultiplexing
Jitter

Cite this

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title = "622Mb/s CMOS clock recovery PLL with time-interleaved phase detector array",
abstract = "A 622Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8μ CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200mW with a single 5V supply, whose core occupies 800×900μ2. RMS jitter of the recovered 78MHz clock is 46ps (0.36{\%}).",
author = "Inyeo Lee and Changsik Yoo and Wonchan Kim and Sanghoon Chai and Wonchul Song",
year = "1996",
month = "2",
day = "1",
language = "English",
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pages = "198--199",
journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
issn = "0193-6530",

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622Mb/s CMOS clock recovery PLL with time-interleaved phase detector array. / Lee, Inyeo; Yoo, Changsik; Kim, Wonchan; Chai, Sanghoon; Song, Wonchul.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 39, 01.02.1996, p. 198-199.

Research output: Contribution to journalConference article

TY - JOUR

T1 - 622Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

AU - Lee, Inyeo

AU - Yoo, Changsik

AU - Kim, Wonchan

AU - Chai, Sanghoon

AU - Song, Wonchul

PY - 1996/2/1

Y1 - 1996/2/1

N2 - A 622Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8μ CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200mW with a single 5V supply, whose core occupies 800×900μ2. RMS jitter of the recovered 78MHz clock is 46ps (0.36%).

AB - A 622Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8μ CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200mW with a single 5V supply, whose core occupies 800×900μ2. RMS jitter of the recovered 78MHz clock is 46ps (0.36%).

UR - http://www.scopus.com/inward/record.url?scp=0030081924&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030081924

VL - 39

SP - 198

EP - 199

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

ER -