• 385 Citations
  • 11 h-Index
20092019
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Fingerprint Dive into the research topics where Yongjun Park is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 3 Similar Profiles
Particle accelerators Engineering & Materials Science
Data storage equipment Engineering & Materials Science
Multitasking Engineering & Materials Science
Program processors Engineering & Materials Science
Reconfigurable architectures Engineering & Materials Science
Hardware Engineering & Materials Science
Cache Mathematics
Throughput Engineering & Materials Science

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Research Output 2009 2019

  • 385 Citations
  • 11 h-Index
  • 25 Conference contribution
  • 10 Article
  • 2 Conference article
  • 1 Letter

A compiler-based approach for GPGPU performance calibration using TLP modulation (WIP Paper)

Yu, Y., Kang, S. & Park, Y., 2019 Jun 23, LCTES 2019 - Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, co-located with PLDI 2019. Chen, J-J. & Shrivastava, A. (eds.). Association for Computing Machinery, p. 193-197 5 p. (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)).

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Modulation
Calibration
Graphics processing unit
Storage allocation (computer)
Limiters

Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs

Oh, Y., Kim, K., Yoon, M. K., Park, J. H., Park, Y., Annavaram, M. & Ro, W. W., 2019 Apr 1, In : IEEE Transactions on Computers. 68, 4, p. 609-616 8 p., 8515055.

Research output: Contribution to journalArticleResearchpeer-review

Prefetching
Cache
Scheduling
Hits
Line

Automated Neural Network Accelerator Generation Framework for Multiple Neural Network Applications

Lee, I., Hong, S., Ryu, G. & Park, Y., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 2287-2290 4 p. 8650190. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Particle accelerators
Neural networks
Field programmable gate arrays (FPGA)
Data communication systems
Hardware

Core-level DVFS for Spatial Multitasking GPUs

Cha, J., Kim, J. & Park, Y., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 1525-1528 4 p. 8650072. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Multitasking
Core levels
Electric potential
Simulators
Clocks

GATE: A generalized dataflow-level approximation tuning engine for data parallel architectures

Kang, S., Yu, Y., Kim, J. & Park, Y., 2019 Jun 2, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a24. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

Parallel architectures
Parallel Architectures
Data Flow
Tuning
Engine